(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming buried contacts.
(2) Description of Prior Art
Very large scale integrated circuit (VLSI) technology comprises the formation of isolated semiconductor devices within the surface of silicon wafers and interconnecting these devices with wiring layers above the surface. This interconnection system usually consists of two or more levels of interconnection metallurgy, separated by insulation layers. The first level of interconnection is used to define small fundamental circuits, for example, a simple TTL gate comprised of two bi-polar transistors and two resistors. The basic CMOS inverter requires that the gates on the NMOS (n-channel MOS field-effect-transistor) and the PMOS (p-channel MOS field-effect-transistor) devices be connected together. Memory cells, in particular, require several such local interconnections.
The progressive need for higher densities of memory cells has fueled the development of that segment of interconnection technology which has become known as "Local Interconnects" (LI). The success and extensive use of polysilicon as the MOSFET gate material has played a dominant role in this development and, in the sub-micron technology of today, it has become the most important material used for forming these connections. Previous technology used an aluminum alloy for short wiring runs such as from a gate electrode to an adjacent drain. These links were referred to as butted contacts because the contact window was opened to expose both the polysilicon gate and the adjacent drain. With the buried contact, direct contact is made between polysilicon and the substrate. When in-situ doped polysilicon is deposited over a thin gate oxide layer to form a transistor gate it can simultaneously be deposited into an opening in the gate oxide over a nearby drain diffusion, for example, to make a contact between the gate and the drain region. Subsequent annealing then forms a stable ohmic contact to the diffused region.
Several major designs for Static Random Access Memory (SRAM) arrays have been developed using both NMOS and CMOS technology. All make abundant use of local interconnects with buried contacts. The earliest, NMOS SRAMs, contained six n-channel MOSFETs (MOS field-effect-transistor) per cell. Three local interconnects using buried contacts were used in this cell to connect polysilicon gates to substrate diffusions.
Other SRAM designs, such as full CMOS SRAMS and poly-load SRAMs, rely upon local interconnects made with buried contacts. These interconnects contribute to a reduction in cell size, allowing an increase in memory density.
A conventional sequence of steps for forming a gate-to-drain LI using a polysilicon buried contact is shown in FIG. 2. Referring first to FIG. 1A, a p-type silicon wafer 10 is provided having a field isolation region (FOX) 16 and a gate oxide 12. A thin layer of about 450 to 550 Angstroms of un-doped polysilicon 14 is deposited using Low-Pressure-Chemical-Vapor-Deposition (LPCVD). Photoresist 18 is applied and openings for the buried contacts are patterned in the resist. Using Reactive-Ion-Etching (RIE) with chlorine, the polysilicon is etched to the underlying the gate oxide which is then removed with dilute hydrofluoric acid or by RIE with tetrafluoromethane (CF.sub.4).
Referring next to FIG. 1B, the wafer is first implanted with boron using the Large-Angle-Tilt-Implanted-Punchthrough-Stopper (LATIPS) process. The implanted boron 24 prevents punchthrough below the channel region and also acts as a channel-stop under the field isolation 16. Next a normal implant of phosphorous of about 1.times.10.sup.15 to 3.times.10.sup.15 atoms/cm.sup.2 forms the region 26 within the silicon where the LI contact is to be made. A second layer of polysilicon 20 is then deposited by CVD (FIG. IC). This layer is in-situ doped with phosphorous and will form the body of the LI as well as the gate electrode for the device. A second layer of photoresist 22 defines the LI as well as the gate electrode.
Again, using RIE with chlorine, the excess polysilicon is etched away forming the completed LI 34 and the gate electrode 32 (FIG. 1D-E). Connection of the LI 34 to the gate shown 32, or to another gate can occur over the field oxide region 16 where additional connections may also be formed. In FIGS. 1D and 1E there is shown the effect of a slight mis-alignment of the photomask which defines the LIs and gates with respect to the photomask which defines the buried contact opening. When the polysilicon is etched back, the subjacent silicon oxide layer 12A acts as an etch stop for the chlorine RIE. A mask mis-alignment can present a small portion of exposed silicon where the oxide had been previously etched away to expose the buried contact. The result is a penetration of the silicon surface 28 during the second polysilicon 20 etch. This penetration has the potential of causing an open or highly resistive contact, especially in shallow implanted devices. Note: if an oxide spacer 36 is used to create lightly-doped-drain (LDD) regions for the transistor, the region at the notch 28 will be even more jeopardized by the lack of dopant at the defect. (The LDD profile is denoted by the dashed portion in FIG. 1E).
The source and drain regions 30 as well as the polysilicon gates 32 are next implanted with phosphorous in the usual manner to complete the formation the self-aligned-polysilicon-gate MOSFETS. A subsequent thermal anneal fuses the contacts and activates the implanted dopants.
FIG. 1E shows the complete implanted drain region which consists of the implants 26 and 30. The actual contact area between the polysilicon LI 34 and the implanted region is smaller than the overall n+ region in the silicon. As device geometries shrink, this area becomes so small that contact resistances increase to unacceptable levels. Additionally, the hazards of mis-alignment become more serious with shallow junction active areas.
This invention describes a method whereby the contact area of the LI to the silicon wafer can be substantially increased without sacrificing planar device design area. Additionally, mis-alignment is made conspicuously more tolerable.